The present invention relates to x-ray sensing detectors, in particular, it relates to a process for fabrication of such detectors.
Efforts have been made to replace x-ray film in radiology through the use of x-ray intensifiers, video cameras, displays, and non-film detectors. One such system employs a scintillation crystal to convert x-rays to corresponding visible light radiation, "Digital Slot Radiography Based on a Linear X-Ray Image Intensifier and Two-Dimensional Image Sensors," Beerlage, Levels, and Mulder, SPIE Vol. 626 Medicine, XIV/PACS IV 161-169 (1986). A photodetector is then used to generate an electrical signal corresponding to the intensity of the visible light radiation. The electrical signal from the detector is converted to digital data and stored in a memory device or electrically displayed, such as on a cathode array tube.
Solid state detectors have also been used in x-ray astronomy. One such detector system was reported in "Multi-Element Self-Scanned Mosaic Sensors," Weimer et al, IEEE Spectrum, Mar. 1969, pages 52-65. The system included an array consisting of a matrix of photodiodes which are charged by light to produce electron-hole pairs.
The Catchpole et al U.S. Pat. No. 4,675,739 describes an incident radiation solid state sensing array made of photosensing elements. Each photosensing element includes back-two-back-diodes, one a photo responsive diode and the other a blocking diode. Each of the diodes has an associated capacitance formed by its electrodes. The magnitude of the charge remaining on a given capacitor is sensed and relates back to the intensity of the incident radiation impinging upon the photosensitive diode. Furthermore, in such a linear photodiode array, the scanning time is so long that real time read-out is made impractical. In addition, the linear photodiode array has to be moved to obtain a two-dimensional image.
Another solid state sensing array includes charge-coupled devices. Charge-coupled devices have a layer of relatively conductive semi-conductor material separated from a layer containing electrodes by an insulator in a two-dimensional image sensing array. However, charge-coupled devices can presently be produced at a format of only less than one inch by one inch. Larger formats of arrays have charge transfer problems due to the number of defective devices that can exist in one line of the array. A defective device in one line of the array can result in a charge not being transferred through that line in the array.
The Nishiki et al U.S. Pat. No. 4,689,487 describes the use of a large area solid state detector (40 cm.times.40 cm). This solid state detector includes pixels in 2,000.times.2,000 matrix form. Each pixel consists of a photodiode conductively connected in parallel to a capacitor which are both then conductively connected to the drain of a metal oxide semi-conductor field effect transistor (MOSFET). The photodiodes are of a polycrystalline or amorphous silicon material.
The Berger et al U.S. Pat. No. 4,810,881 describes an amorphous silicon detector of 36 cm.times.43 cm. Each pixel in the detector includes an amorphous silicon diode that is conductively connected in series to a capacitor which in turn are both then conductively connected to the drain of an amorphous silicon-based junction field effect transistor.
In any fabrication process of making large area solid state detectors, the number of microlithography masking steps plays a critical role in determining the yield of usable detector devices, and hence the commercial viability of such devices. Solid state detector devices that include photodiodes and thin-film transistors (TFTs) require a high number of microlithography masking steps. For example, 16 masking steps may be required to produce a DRAM (Dynamic Random Access Memory) device and nine to ten steps to produce a liquid crystal display device. The yield Y for such devices is proportional to Y.sup.a, where Y is the yield for each individual masking step, and n is the number of masking steps. The yield may also be defined by Y=e.sup.-29AD where A is the chip area and D is the defect density defined as defects per square centimeter. A high number of microlithography steps will cause more defects and large area will create a lowering in yield. Principles of CMOS VLSI Design, Neil Weste, and Kamran Eshraghian, Addison-Wesley Publishing Co., pg. 156. It will be appreciated that the alignment during masking must be exact due to the small area of each pixel, for example, 85 .mu.m.times.85 .mu.m. Misalignment of the masks can occur easily and result in a short in the device.